MTS Verification Engineering - #941433
Rambus Chip Technologies
Develop test plans, tests and verification infrastructure for complex Block level / IP / Sub-system.
Create verification environment using UVM methodology.
Create reusable bus functional models, monitors, checkers and scoreboards.
Drive functional coverage driven verification closure.
Work with architects, designers and post-silicon teams
Bachelors/Masters degree in Electronics/Electrical Engineering.
2+ years of verification experience.
Significant experience in HVL based verification with 4+ years expertise in SV & OVM.
Experience in I2C/I3C Protocol & DDR3/4/5 memory protocol knowledge.
Good understanding of memory technology, memory sub-system.
Should have created Testbench architectures, as well as build verification setup from scratch to ensuring successful verification closure of reasonably complex designs.
Should have knowledge on all aspects of verification components & verification closure.
Should have flair for documentation, defining/improving methodology and achieving productivity improvement.
Ability to provide technical guidance & resolving technical conflicts desired.
Ability to communicate technical and project issues to business and technical senior management.
MUST have very good verbal and written communication skills.