Engineer - DV
Quest Global
Key Responsibilities:
Develop and execute verification plans for digital designs.
Create and maintain SystemVerilog/UVM testbenches.
Develop directed and random test cases.
Perform functional, code, and assertion coverage analysis.
Debug simulation failures and identify root causes.
Work closely with Design, Architecture, and Validation teams.
Ensure verification closure and quality sign-off of IP/SoC designs.
Support regression execution and result analysis.
Work Experience
Required Skills:
Strong knowledge of Verilog/SystemVerilog.
Experience with UVM methodology.
Good understanding of digital design fundamentals.
Familiarity with protocols such as AXI, AHB, APB, SPI, PCIe, DDR, etc.
Experience with simulation/debug tools such as VCS, Questa, Xcelium, Verdi.
Strong debugging and problem-solving skills.