Verification Engineer - Memory Subsystem
NVIDIA
What You’ll Be Doing
- Responsibility includes verifying the design, architecture and micro-architecture using sophisticated verification methodologies
- Work on the development of the verification infrastructure components (functional models/scoreboards/setting up new verification environments) for complex IPs using UVM methodology
- Define the verification scope, develop testplans and work on functional coverage driven verification closure
- Collaborate with architects, designers, software engineers, post-silicon teams across sites for innovative and timely solutions
- BS /MS in EE/ECE with 2+ years of experience
- Exposure to verification closure of complex IP/sub-system for at least one project
- Expertise in industry-standard verification flows like SV random testing, UVM, FV, coverage metrics, profiling tools, X prop, etc.
- Strong coding skills in SV
- Passion for debugging and good problem solving skills
- Strong communication and interpersonal skills
- Prior verification experience related to memory subsystem/network interconnect IPs is a huge plus
- Familiarity with memory subsystem concepts such as cache coherency, memory consistency models, arbitration policies, high-speed IO protocols and/or on-chip interconnect
- Familiar with scripting languages (Perl/python).
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