Interesting Job Opportunity: Sykatiya Technologies - RTL Design Engineer - Verilog/ASIC
Sykatiya Technologies Pvt Ltd
Remote
Please share me your updated profile.
We are very glad to connect with you and understand your aspirations and move forward.
Jd
Skill : RTL Design Engineer
Experience : 3- 10 Yrs
Location : Bangalore
- Sound knowledge of RTL design with Verilog/system Verilog and front-end design tools & flows
- Good experience in Synthesis & Timing Analysis required
- Experience in developing Micro architecture from specifications and take it upto RTL coding and synthesis.
- Should have worked on IP and SoC level Synthesis for multiple generations and be familiar with problems associated with different Process technologies
- Should have experience working on Low power synthesis and understands UPF
- Experience in implementing ECOs
- IP development and coding using standard coding guide lines
- Must have strong knowledge of AMBA AHB/AXI protocol
- Working knowledge on code coverage, functional coverage, Lint, CDC, Formality etc
- References are most appreciate -
(ref:hirist.tech)