ASIC Engineer, Design Verification

Meta

Meta is hiring Application-Specific Integrated Circuit (ASIC) Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a team working with experienced engineers across the industry, focused on developing ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure. Along with traditional simulation, use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

ASIC Engineer, Design Verification Responsibilities:

Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Debug, root-cause and resolve functional failures in the design, partnering with the Design team
Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring design quality meets defined verification criteria
Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry

Minimum Qualifications:

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
2+ years of experience in SystemVerilog/UVM (Universal Verification Methodology) and/or C/C++ based verification
Experience in one or more of the following areas along with functional verification - System Verilog Assertions, Formal, Emulation
Experience in EDA/Electronic Design Automation tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

Preferred Qualifications:

2+ years experience in IP/sub-system and/or SoC (System on Chip) level verification based on SystemVerilog UVM and OVM (Open Verification Methodology) based methodologies
2+ years of experience in development of UVM based verification environments from scratch
Experience in ASIC Development life cycles
Experience with verification of ARM/RISC-V based sub-systems or SoC (Systems on Chip)
Experience working across and building relationships with cross-functional design, model and emulation teams
Experience with Design verification of Data-center applications like Video, Artificial Intelligence/Machine Learning (AI/ML) and Networking designs
Experience with IP or integration verification of high-speed interfaces like AMBA, PCIe (Peripheral Component Interconnect Express), DDR (Double Data Rate), Ethernet
Experience with revision control systems like Mercurial, Git or SVN

About Meta:

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.