Director , Engineering (GPU Physical Design)

Qualcomm

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Minimum Qualifications:

Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.

OR

Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

Minimum Qualifications

Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution
20+ years of experience in Physical Design/Implementation
10 years of experience in leading a team working on high performance cores

Minimum Requirements:

Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization.
Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions.
Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts
Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes
Good understanding of clocking architecture.
Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc.
Well versed with Tcl/Perl Scripting
Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers.
Strong problem-solving skills and good communication skills.

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