Senior PD Engineer (BB812FI RM 4534)
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Role Overview
Hiring Senior Physical Design Engineers to take the largest, most macro-dense, high-frequency blocks and subsystems from netlist to GDSII at 3nm. This PD engineer will own block-level closure end to end and work daily with RTL, architecture, DFT, CAD and package teams.
Key Responsibilities
- Own block-level PnR from floorplan to GDSII on multi-million-instance, macro-dense 3nm partitions.
- Define floorplans, macro placement, power grid and pin/feedthrough strategy that make congestion and timing converge early.
- Close multi-GHz timing: CTS (useful skew, multi-source or mesh where needed), OCV/POCV, SI and post-route optimization.
- Drive signoff: IR/EM, DRC/LVS, antenna, ECO and metal-fill to tape-out.
- Build TCL/Python automation and flow improvements that raise QoR and cut turnaround.
- Partner with architecture, RTL, DFT and CAD on partitioning, constraints and PPA trade-offs; report status and risks.
- 8–12 years of physical design experience (7 minimum); BE/BTech or MS in Electrical or Electronics Engineering.
- Hands-on 3nm (TSMC N3E/N3P or equivalent) block-level implementation through tape-out. Clock-only, CAD-only or ECO-only roles do not count.
- Full-flow ownership of large, macro-dense blocks that meet the scale and frequency bar below.
- Strong in Synopsys Fusion Compiler or ICC2, or Cadence Innovus; PrimeTime, StarRC or Quantus; Calibre; RedHawk or Voltus.
- Fluent in TCL and Python (Perl or Shell is a plus); able to debug flow and QoR issues from logs.
- Subsystem or top-level integration, hierarchical flows and partition budgeting.
- Experience on high-speed networking, AI accelerator or SerDes-adjacent silicon.
- Multi-voltage (UPF) implementation and low-power closure at 3nm.
- 2nm exposure, or technical lead experience mentoring 3+ engineers.