Design Verification Engineer

DECCANX

Design Verification Engineers prove that a design does what its specification says, and find out loudly when it does not.

Our flow uses SystemVerilog and UVM with constrained-random stimulus, scoreboards, assertions and functional coverage, as in the NX-AXI DMA engine verification plan.

What you will work on

Read specifications and write a verification plan with testable features
Build UVM components: agents, drivers, monitors, scoreboards and sequences
Write directed and constrained-random tests and SystemVerilog assertions
Define and close functional and code coverage; explain every hole
Debug failures to root cause and file clear bug reports
Maintain regression scripts and report results honestly

Skills Required And How Deep

Depth shows how far along you should be on day one. We teach the rest.

SystemVerilog for verification (classes, randomisation)Strong

Testbenches are object-oriented code

UVM methodology basicsWorking knowledge

Our environments are UVM; you will extend them from week one

Digital design fundamentalsStrong

You cannot verify what you cannot understand

Assertions and coverage conceptsWorking knowledge

Evidence of completeness comes from coverage and checks

Debugging disciplineStrong

Most of the job is finding why a test failed

Scripting in Python or MakeWorking knowledge

Regression flows are scripted

Nice to have

A UVM mini-project
Protocol knowledge such as AXI
Experience reading waveforms in a commercial simulator

Tools you will use

SystemVerilog
UVM
Questa or compatible simulators
SVA
Python
Make

What you will learn

Building a reusable UVM environment
Writing a verification plan that a reviewer can audit
Closing coverage with evidence rather than optimism

Your first 90 days

First 30 daysLearn the existing environment and run the regression; fix one small test.
Days 31 to 60Add a new sequence and checker; find your first real bug.
Days 61 to 90Own a feature area from plan to coverage closure.

Who fits: You are the person who asks 'but what if this happens?' and enjoys proving yourself wrong.