Sr. Staff Engineer, STA – SoC Timing Lead
Sandisk
Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.
Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.
Description
Sr. Staff Engineer, STA – SoC Timing Lead
Function: ASIC Design / Physical Design – Signoff | Location: [Bangalore]
Role Summary
Own SoC-level static timing analysis and timing signoff for advanced-node ASICs, from constraint development through timing closure and tape-out. You will lead the chip-level timing strategy across blocks, partitions and corners, and drive convergence with Physical Design. You will work with Architecture, RTL, DFT, Physical Design, Package, SI/PI, IP and Foundry teams.
Key Responsibilities
- Timing strategy and signoff: Define the SoC timing methodology, corner and mode strategy, and signoff criteria. Own full-chip STA signoff for setup, hold, and design-rule checks (max transition, max capacitance, min pulse width).
- Constraints: Own top-level SDC development and quality. Cover clocks, generated clocks, I/O, exceptions and CDC/RDC constraint intent. Drive constraint reviews and sign-off with RTL, DFT and IP teams.
- Hierarchical timing: Define block and subsystem budgets, interface timing models (ETM/ILM) and partition-level hand-offs. Manage timing consistency across hierarchy.
- Convergence and ECO: Analyze violations, debug root causes, and drive timing closure and ECO strategy with PD. Manage closure through final signoff.
- Variation and accuracy: Apply on-chip variation (OCV/AOCV/POCV), SI/crosstalk, and IR-aware timing analysis. Resolve pessimism versus risk tradeoffs.
- Voltage and margin methodology: Define voltage-aware timing signoff, including Vmin and typical/fast-corner signoff. Align voltage specs with Design, PETE and Product teams.
- Interfaces: Close timing on high-speed and source-synchronous interfaces (e.g., DDR, PCIe, die-to-die) with the IP and PHY teams.
- Flow and methodology: Develop and automate STA flows, scripts and checks. Drive regressions, dashboards and signoff checklists, and evaluate new tools and techniques.
- Leadership: Lead and mentor timing engineers, set technical direction, and manage schedule and risk. Interface with Foundry and EDA vendors, and report status to program and management teams.
- BS/MS in Electrical Engineering or a related field.
- 12+ years in ASIC STA and timing signoff, including several full-chip tape-outs at advanced nodes (7nm and below preferred).
- Strong command of SDC, MCMM, OCV/POCV, SI-aware STA and hierarchical timing.
- Experience leading chip-level timing closure and ECO convergence with PD.
- Tools: PrimeTime (PX/SI), Tempus, and constraint and CDC tools.
- Scripting in Tcl, Python or Perl.
- Preferred: Voltage-aware and Vmin signoff, multi-die or 2.5D/3D timing, high-speed interface timing, and timing signoff methodology development.
Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.
Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.